This invention relates generally to flash EEPROM system integrated circuits, and, more specifically, to techniques for controlling the making such circuits that improve the accuracy and reproducibility of the circuit structures and their operation.
As is well known, flash EEPROM systems provide non-volatile storage of data in memory cells formed of a field effect transistor which individually have an electrically isolated floating gate, a control gate and source and drain implants in the substrate. The cell is programmed by injecting a controlled amount of charge onto the floating gate. The cell is later read by application of an appropriate set of voltages to the control gate, source and drain, and then by monitoring some parameter that varies in relation to the amount of charge on the floating gate. This parameter is usually the amount of current flowing through the cell for fixed voltages on the control gate, source and drain, but can be some other parameter such as the amount control gate voltage that causes the cell to conduct some defined level of current. Example disclosures of these techniques are found in U.S. Pat. Nos. 5,095,344, 5,172,338, and copending patent application Ser. No. 08/910,947, filed Aug. 7, 1997, entitled xe2x80x9cNovel Multi-State Memory,xe2x80x9d each of which is incorporated herein by this reference.
A typical flash EEPROM includes an array of floating gates positioned across a semiconductor substrate over a channel region between adjacent source and drain implants. The floating gate extends over the entire length of the channel in one type of device, and over only a portion of it in another type. In this later type, the control gate is positioned over the remaining length of the channel to form a select transistor in series with the floating gate transistor, a xe2x80x9csplit-channelxe2x80x9d type of device. In either case, the array is constructed by forming various gate and field dielectric layers across appropriate regions of the substrate, a first polysilicon layer that is separated to become the floating gate array and a second polysilicon layer for the control gates, in a large number of individual steps necessitated by the complex nature of the structures. Examples of such structures and manufacturing techniques are given in U.S. Pat. Nos. 5,070,032, 5,343,063, 5,554,553, 5,661,053, 5,579,259 and 5,712,179, each of which is incorporated herein by this reference.
In order to store binary data, a majority of flash EEPROM systems divide the monitored parameter into two ranges separated by a single breakpoint level. Each cell then stores one bit of data. A cell is programmed into one of the two ranges by injecting charge onto the floating gate until it is verified, as part of the programming process, that the cell has been programmed into the desired range. More recently, in order to increase the density of data stored in a flash EEPROM, more that one bit of data is being stored in each cell by increasing the number of ranges of the monitored parameter to something above two. For example, one product uses four ranges, established by defining three breakpoint levels of the monitored parameter, to store two bits of data per cell. Example disclosures of such multi-state systems include U.S. Pat. Nos. 5,043,940 and 5,163,021, which are incorporated herein by this reference. An important goal of current flash EEPROM development efforts is to further increase the number of discrete states into which each cell can be programmed and thus read, in order to store more than two bits per cell. Eight distinct states, for example, allows three bits to be stored in each cell, sixteen states stores four bits per cell, and so on.
As the number of programmable states of each cell increases, however, the extent of each range becomes smaller. For example, if the monitored parameter is cell current, there is only a certain overall range of cell current in which the cell is operable, often termed an xe2x80x9coperating windowxe2x80x9d. As this window is divided into smaller and smaller parts, as the amount of data stored in each cell increases, the extent of each range necessarily becomes less. This then requires an increased accuracy and resolution in programming and reading the states of the cells. As a result, effort is being directed to more accurate programming and reading system operating techniques. An example is described in copending patent application Ser. No. 09/177,809, filed by Cernea et al. on Oct. 23, 1998, and entitled xe2x80x9cNon-Volatile Memory with Improved Sensing and Method Therefor,xe2x80x9d now U.S. Pat. No. 6,044,019, which is incorporated herein by this reference.
It is a primary object of the present invention to provide improvements that allow a flash EEPROM integrated circuit system to be accurately and reproducibly operated with an increased number of storage states per cell.
It is a further object of the present invention to provide improved cell structures and manufacturing techniques.
These and additional objects are accomplished by the present invention, which includes the realization that a considerable portion of the inaccuracy and variability of operation between flash EEPROM cells on one chip, and those on different chips, that have created a limitation upon the number of programming states in which the cells may be operated, are due to changes in dimensions of certain elements that unintentionally occur as a result of processing steps taking place after formation of those elements. In particular, as a principal example, further growth of the floating gate oxide layers at their edges under the floating gates, which occurs as the result of subsequent oxidation steps used to grow other oxide layers and the like, causes the effective width of the cell channel to be decreased and thus change the operating characteristics of the cell from what is expected. Not only can this undesired decrease in channel width be different among cells on one chip, or between cells on different chips from wafers of different processing runs, its decrease causes other variabilities of the cell structure to take on greater significance in their operating characteristics. As another example, the further oxidation steps consume material on the sides of the polysilicon floating gate which can result in a narrowing of channel width, and of the control gate which, in the case of a split-channel cell, affects the width of the channel in the select transistor portion of the cell.
These unintended dimensional changes are significantly reduced, and can be eliminated altogether, as a result of the present invention, wherein barriers are formed to block oxygen from reaching the floating gate oxide and polysilicon gate walls during as many of the subsequent oxidation steps as practical, preferably all of them. The barrier is preferably formed from a dielectric material that is deposited in a normal manner. Silicon nitride is one such material. It also preferable that the oxygen barrier be provided by an element that already exists in an appropriate position of the structure, by simply changing the material to an oxygen blocking material, in order to avoid adding new processing steps.
In specific embodiments implementing the present invention, silicon nitride is used in place of field oxide and/or as the material used to form spacers that abut the floating gates and gate oxide underneath the floating gates. In an alternative embodiment, a silicon nitride layer is formed under the field oxide by adding at least one additional processing step.
In a further embodiment, a layer used to form dielectric spacers is made of an oxygen barrier material, such as silicon nitride. This layer is then left in place over the memory cell array portion of the chip during formation of peripheral circuits adjacent the memory array, at least during the step of growing gate oxide for the peripheral transistors. The oxygen barrier dielectric material layer is thereafter etched in a manner to leave the desired side wall spacers. It has been found that the peripheral transistor gate oxide growing step causes, by itself, much of the adverse effect on the memory cell gate oxide layers that is described above. This adverse effect is substantially eliminated by maintaining an oxygen barrier layer in place over partially formed memory cells during at least some processing of peripheral elements when it would otherwise normally be earlier removed in whole or in part to form the memory cell array.
Additional objects, advantages and features of the various aspects of the present invention are given in the following description of its preferred embodiments, which description should be read in conjunction with the accompanying drawings.